In the last post two posts on semiconductor design I reviewed the risks to Altera and Xilinx due to competition from other platforms, existing competitors, and new entrants. Here I’ll review the risks from reliance on the communication sector (which may finally be a strength for the first time since early 2000) and from ASIC vendors.
Competition from Structured ASICS and ASSP’s
In March 2006, LSI Logic, the first vendor to create a structured ASIC, closed its RapidChip division exiting the structured ASIC business. This was a blow to the EDA vendors who haven’t seen significant growth since the 2001 downturn and have struggled to gain a foothold in the FPGA industry. By shuttering its structured ASIC division LSI conceded that customers are moving to FPGA’s for new products as it is much faster and more economical to initially design a Xilinx (or Altera) FPGA and migrate to the same vendor’s structured ASIC in volume, than design using LSI’s ASIC-based process.
In 2001, Altera introduced their HardCopy® structured ASIC platform and they are now a leader in the structured ASIC market. Altera has a straightforward migration path from FPGA to structured ASIC. They maintain compatibility with the FPGA architecture, but reduce the die size by removing the configuration circuitry, programmable routing, and programmability for logic and memory with fixed wired interconnect. Xilinx has a similar product called EasyPath®.
Reliance on Communications Sector
In 2000, over 80% of PLDs went into communications related equipment. Today that number is just under 50% of sales and steadily dropping. Since 2000 the growth in PLDs for communications end products has significantly trailed other end markets.
In fact, if the growth in the communication sector picks up, like we think it will in 2010 or 2011, this could be a major boost to the PLD market. The other end market segments like storage, industrial, and consumer electronics should continue to see strong growth over the next decade.
The ASIC (Application Specific Integrated Circuit) Market
ASIC’s must be designed for a specific end product. These design and manufacturing costs have risen rapidly over the years as the geometry of semiconductors has gone from the millimeter to the nanometer level. The semiconductor manufacturing machines must be set for each ASIC, referred to as non-recurring engineering costs. Any bugs discovered after manufacturing an ASIC must be fixed with much slower software or the ASIC must be completely re-manufactured.
Since the complexity of designing an ASIC has increased dramatically many companies have outsourced ASIC design to third party firms which complicates IP ownership and potentially involves outsourcing what should be a core competency. As complexity, cost, and time to market has increased companies are looking to alternatives when building their digital products.
PLD’s are designed and manufactured once. Customers then write the software that these PLD’s will use. Generic or one time programmable processors are similar standardized IC that the customer uses to process the software it has written. By using a simpler PLD or generic processor it eases a company’s ability to in-source all of a product’s design while shrinking the time spent on product design and testing.
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Characteristics
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ASIC
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ASSP
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PLD
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Custom Processor / DSP
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Generic Processor
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Customer’s Development Cost
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Very High
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Low
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Moderate
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High
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Moderate
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Average Selling Prices (ASP)
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Low
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Low to Moderate
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Moderate to High
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Low to Moderate
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Low to Moderate
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Time to Market
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Slow
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Moderate
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Fast
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Slow
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Fast
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Customizable
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Yes
(by manufacturer)
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No
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Yes
(by customer)
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No
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Yes, only one time
(by customer)
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Updatable in the field
(smooth product updates)
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No
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No
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Yes
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No
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No
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Performance
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Very High
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High
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Moderate
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Low to Moderate
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Very Low
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Clearly there is a tradeoff between speed (time to market), performance, and flexibility. The Cost-benefit of high-end PLD chips improves as small-geometry processes bring costs down while complexity of submicron designs increases cost of developing ASIC chips. The number of new ASIC starts has decreased from 12,000 in 1995 to 2,000 in 2002 and may not exceed 1,000 in 2008.
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ASICs, typically require weeks to develop, plus have large up-front engineering costs
- It can take a year to design an ASIC, plus more time to design into end equipment
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PLD’s allow designers to adapt to changes in design throughout overall design process (from prototyping to production)
- An engineer can design and program a high-density PLD in a matter of hours
- Bugs and glitches can be fixed during early production
- Features and functionality can be added while the product is deployed in the field
- The ASIC market has far fewer design starts, but the ASIC designers typically have much larger budgets
The advantages of FPGAs over ASICs and ASSPs are design and product flexibility allowing users to reduce a products’ time to market and avoid high up-front cost of developing custom solutions. The disadvantages of FPGAs are higher unit costs than custom solutions and they also use more energy affecting battery life.
One of the next big growth markets for semiconductors is in the SoC / embedded market. On what devices will the next group of innovators and inventors build their products? Xilinx and Altera (along with one-time programmable processor maker Microchip) have the early edge; with the industries goliaths Intel, IBM, and TI currently offering less flexible products and development platforms. Who the semiconductor intellectual property vendors and end-product innovators embrace will determine which platform overtakes the shrinking market for product specific semiconductor devices (aka ASICs, ASSPs, etc).
